High performance RISC processor for convolution using pipelining


  • Gangaramulu Kumbam1, Sandeep Chilumula2 1 PG Scholar, M.Tech VLSI System Design, Vidya Jyothi Institute of Technology, Hyderabad, India Associate Professor, Department of ECE, Vidya Jyothi Institute of Technology, Hyderabad, India


Many algorithms have been design in order to accomplish and improve performance of the filters by using the convolution design. The architecture of the proposed RISCCPU is a uniform 32-bit instruction format, single cycle non-pipelined processor. It has load/store architecture, where the operations will only be performed on registers, and not on memory locations. A total of 27 instructions are designed in initial development step of the processor. The instruction set consists of Logical, Immediate, Jump, Load, store and HAL Type of instruction. The advantages of RISC processor and operation specific design possibilities have been analyzed.

In this paper we have implemented 32 bit RISC processor to perform circular convolution at different modules of RISC processor like execute unit along with ALU, Instruction fetch along with instruction memory, decode unit, resistor unit, data memory has been implemented. For performance improvement apply the pipeline stages to the   RISC architecture, n this paper we proposed the 5 stages and 6-stage pipeline RISC processor and comparing the both pipeline stages.




How to Cite

Chilumula2, G. K. S. (2017). High performance RISC processor for convolution using pipelining. International Journal of Engineering Science and Generic Research, 3(3). Retrieved from https://www.ijesar.in/index.php/ijesar/article/view/68