Yield Enhancement Techniques of VLSI Technology


  • Isha Kashyap1, Jagriti Gupta2 1M.Tech, Jayoti Vidyapeeth University, Jaipur 2Assistant Professor, Jayoti Vidyapeeth University, Jaipur


Several yield Enhancement techniques have been proposed for the last two stages of fabrication. Our approach is based on the ability to improve the yield during integrated circuit fabrication through defect detection and defect reduction. In this paper we have classified the defects on lithography layer of the wafer and then reduced them so as to enhance the yield of an integrated circuit. This is done by optimizing the inspection recipe parameter on defect capture rate. It is possible to improve the yield of an integrated circuit by minimizing the number of defects on it. During the fabrication of an integrated circuit on the wafer there are many steps like lithography, etching, oxidation, deposition, CMP etc through which a single wafer has to go many times, In this whole procedure of fabrication certain particle my fall on wafer or may result in scratches on wafer .These type of defects result in yield loss and may lead to the failure of integrated circuit. Keywords: Wafer, Defects, integrated circuits, Lithography, threshold, focus offset, recipe, defect inspection tool, ORS.




How to Cite

Gupta2, I. K. J. (2016). Yield Enhancement Techniques of VLSI Technology. International Journal of Engineering Science and Generic Research, 2(3). Retrieved from https://www.ijesar.in/index.php/ijesar/article/view/23