2, Shilpa B Darvesh1, T. Kavitha. “Fpga Implementation of High Performance Fully Pipelined Aes Algorithm Using Reversible Logic”. International Journal of Engineering Science and Generic Research 2, no. 3 (June 30, 2016). Accessed February 9, 2026. https://www.ijesar.in/index.php/ijesar/article/view/19.