LAKSHMI, C. S.; RAMARAO, B. Low Power BIST based Multiplier Design and Simulation using FPGA. International Journal of Engineering Science and Generic Research, [S. l.], v. 4, n. 1, 2018. Disponível em: https://www.ijesar.in/index.php/ijesar/article/view/99. Acesso em: 21 aug. 2026.