INTERFACING BETWEEN I2C MASTER AND WISHBONE CONTROLLER

Abstract

I2C bus is a serial communication protocol and stand for Inter-Integrated Circuit is implemented. The I2C bus use to a master and slave, for data transfer. The I2C bus is a popular serial two-wire bus, these two wire can be used in many systems because it has low overhead. These two- wire are minimizes the interconnections of the devices, so ICs are more pins, and the more number of blocks are required on printed circuit board, these can be reduced. This I2C bus is capable of operation at 100 KHz; each and every device is connected to the single bus which has a unique address with master or slave protocol. By using the verilog HDL the interfacing between I2C master with wishbone controller is implemented, and those modules will be synthesized & simulated on the Xilinx ISE 14.2i tool. The availability of the master and slave can performs the high speed of the data transfer. Keywords: Master, Wishbone, SLAVE, SDA, SCL.